DOIONLINE 
DOIONLINE Publish In |
International Journal of Electrical, Electronics and Data Communication (IJEEDC)-IJEEDC |
 Journal Home Volume Issue |
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Issue |
Volume-7,Issue-9 ( Sep, 2019 ) | |||||||||
Paper Title |
Clock-Gating Strategy for Reducing Dynamic Power Dissipation on FPGA | |||||||||
Author Name |
Jisha Varghese, Sreekala Ks | |||||||||
Affilition |
Department of Electronics and Communication Engineering, Saintgits College of Engineering, Kottayam, Kerala, India | |||||||||
Pages |
27-30 | |||||||||
Abstract |
In all silicon devices, power dissipation is one of the major problem which has to be eliminated. Reducing power minimizes the precise needs for cooling, improved durability, longer autonomy in battery operated devices and lower costs. Besides, power also has significant role in choice of the computing platform right at the outset. In case of field-programmable gate arrays (FPGAs), power dissipation is more as compared to equivalent application-specific integrated circuit (ASIC), but often compare favorably to conventional processors used for same functional tasks. Previous Clock-gating methods are not effective in implementation on FPGAs. This work presents a new Course Grained ON-OFF control method that can reduces power especially dynamic power by introducing a clock gating strategy. This work can introduce a technique that aims to achieve power savings by selectively switching off the circuit part when they are not temporarily active by using a Clock enabling circuit. This technique can be adopted for any application and can finally be integrated into the synthesis stage of design flow. Keywords - Clock-Gating, Dataflow, Clock Enabling Circuit | |||||||||
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