DOIONLINE 
DOIONLINE Publish In |
International Journal of Electrical, Electronics and Data Communication (IJEEDC)-IJEEDC |
 Journal Home Volume Issue |
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Issue |
Volume-3, Issue-1 ( Jan, 2015 ) | |||||||||
Paper Title |
Code-Driven Boundary Scan Testing | |||||||||
Author Name |
Salim A. Jayousi, Mohd Saufee Muhammad | |||||||||
Affilition |
Department of Electrical and Electronic Engineering, University Malaysia Sarawak, Malaysia | |||||||||
Pages |
40-43 | |||||||||
Abstract |
During the last few years, integrated circuits (ICs) manufacturing was developed to be more compatible with “Design for Testability (DFT)” features. New embedded circuits were interpolated inside IC wafers. Such new additions increased the IC design complexity and as a result, the manufacturing overheads also increased. In this paper we introduce a new technique for testing onboard ICs with less embedded circuitry inside chips. The new technique depends basically on driving the test process by test code packets. The transmitted test packets have meaningful compartmentalized pieces of information which are capable to control all test activities. Test access port (TAP) is to be excluded from IC circuitry and shared over the board to serve all ICs together. TAP units activities are totally subjected to the data packet instructions. The design is simulated by NI Multisim software. | |||||||||
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