DOIONLINE 
DOIONLINE Publish In |
International Journal of Electrical, Electronics and Data Communication (IJEEDC)-IJEEDC |
 Journal Home Volume Issue |
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Issue |
Volume-1,Issue-3 ( May, 2013 ) | |||||||||
Paper Title |
Image Processing And Data Hiding Framework On FPGA Based Platform | |||||||||
Author Name |
Shreedeep Gangopadhyay, Bhaskar Banerjee | |||||||||
Affilition |
Techno India, EM 4/1 Salt Lake City, Sector- V, Kolkata | |||||||||
Pages |
77-82 | |||||||||
Abstract |
With the introduction of reconfigurable platform such as Field Programmable Gate Arrays (FPGA) and advent of new high level tools to configure them, image processing on FPGA has emerged as practical solutions for most of computer vision and image processing problems. The use rapid prototyping tools such as MATLAB Simulink and Xilinx System Generator becomes increasingly important because of time-to-market constraints. Image processing has very important application in digital domain ranging from medical application through image enhancement to copy right protection through water marking technique .This project presents a methodology for implementing real-time image processing applications on a reconfigurable logic platform using Xilinx System Generator (XSG) for Matlab. | |||||||||
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