DOIONLINE 
DOIONLINE Publish In |
International Journal of Electrical, Electronics and Data Communication (IJEEDC)-IJEEDC |
 Journal Home Volume Issue |
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Issue |
Volume-2,Issue-11 ( Nov, 2014 ) | |||||||||
Paper Title |
Serial One-Step Majority Logic Decoder For EG-LDPC Code | |||||||||
Author Name |
M.Pramodh Kumar, S.Murali Mohan | |||||||||
Affilition |
Student, Dept of Electronics and Communication Engineering, Sri Venkateswara College of Engineering & Technology (Autonomous), Chittoor, A.P, India Associate Professor, Dept of Electronics and Communication Engineering, Sri Venkateswara College of Engineering & Technology (Autonomous), Chittoor, A.P, India | |||||||||
Pages |
30-35 | |||||||||
Abstract |
In the modern digital system design the reliability and security of memories are essential considerations. As technology scales, memory devices become larger and more powerful error correction codes are needed to protect memories from soft errors. Low Density Parity Check (LDPC) Codes are the class of linear block codes which provide near capacity performance on large collection of data transmission channels while simultaneously feasible for implementable decoders. One specific type of LDPC codes, namely EG- LDPC are used due to their fault secure detection capability, higher reliability and lower area overhead. One of the existing methods for error detection in EG-LDPC is the one step Majority Logic Decoder (MLD) method used to detect the error in memory device itself. | |||||||||
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