DOIONLINE 
DOIONLINE Publish In |
International Journal of Electrical, Electronics and Data Communication (IJEEDC)-IJEEDC |
 Journal Home Volume Issue |
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Issue |
Volume-6,Issue-10 ( Oct, 2018 ) | |||||||||
Paper Title |
Design an Efficient Majority Logic GDI Carry- Select Adder | |||||||||
Author Name |
N. Gopi Chand, S. Baba Fariddin, Sk. Mohiddin | |||||||||
Affilition |
Hod & Associate Professor, Dept of E.C.E, Guntur Engineering College, Guntur, A.P, India. Assistant Professor, Dept of Ece, St.Marys Group of Institutions, Guntur, A.P, India. Assistant Professor, Dept Of E.C.E, Sri Sarathi Institute of Engineering, Nuzvid, A.P, INDIA | |||||||||
Pages |
22-25 | |||||||||
Abstract |
In modern VLSI, CMOS technologies are invented and the size is reducing day by day. So the complexities increases resulting into the high integration. Here a 1 bit and 8 bit Carry Select Adder (CSLA) is proposed to obtain efficient design. By introducing traditional full adder, conventional CSLAs are designed. The complexity obtained in the system is represented from power consumption and area. So this problem is solved by implementing modern technique on the CSLA. Moreover the logic gates are designed which is based on the technique of Gate Diffusion Input (GDI). It can observe that the both area and power consumption is reduced from proposed design. It is shows that the power for 1-bit is reduced and the power for 8-bit is reduced. The simulation results exhibits that the GDI design performs better than the CMOS logic design. Index terms - CSLA(Carry Select Adder (CSLA); GDI (Gate Diffusion Input) Technique; RCA (Ripple Carry Adder). | |||||||||
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