DOIONLINE 
DOIONLINE Publish In |
International Journal of Electrical, Electronics and Data Communication (IJEEDC)-IJEEDC |
 Journal Home Volume Issue |
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Issue |
Volume-6,Issue-10 ( Oct, 2018 ) | |||||||||
Paper Title |
A Novel Design of Bit-Slice Matrix Multiplier for RSFQ using Shadow Latch | |||||||||
Author Name |
T. Prasad Babu, A. Siva Prasad, T. Indira | |||||||||
Affilition |
Head of the Dept., Dept of E.C.E, Bvsr Engineering College, Chimakurthy, Prakasam Dt, A.P Head of the Dept.,, Dept. Of ECE, Chintalapudi Engineering College, Ponnur, Guntur Dt, A.P Assistant Professor, Dept of E.C.E, Narasaraopet Engineering College, Narasaraopeta, Guntur Dt, A.P | |||||||||
Pages |
18-21 | |||||||||
Abstract |
In this paper, we demonstrated a high speed energy efficient approximate multiplier. We contemplate an approach which is to round the operands to nearest exponent to two. The proposed system is applied for both unsigned and signed multiplications. A 4-bit bit-slice matrix multiplier is exploited for 32-bit rapid multiple-flux-quantum (RMFQ) artificial intelligence processor is proposed in this paper. The multiplier mainly includes bit-slice multipliers which is 4-bit and 4-bit bit-slice adders. The unsigned integer matrixes multiplication is contrivance by control signals. The result shows that our method simplifies the circuit complexity, truncates the hardware costs and allows extending the matrix multiplier to a smaller or larger number of bits. Keywords - Accuracy, approximate computing, energy efficient, error analysis, high speed, multiplier. | |||||||||
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