DOIONLINE

DOIONLINE NO - IJEEDC-IRAJ-DOIONLINE-13978

Publish In
International Journal of Electrical, Electronics and Data Communication (IJEEDC)-IJEEDC
Journal Home
Volume Issue
Issue
Volume-6,Issue-10  ( Oct, 2018 )
Paper Title
Memory Based Floating Point FFT Processor using Memory Block Vector
Author Name
S. Butchi Babu, T. Naga Mounika, Hemasri Chundi
Affilition
Assistant Professor, Dept of ECE, Vikas Engineering College, Nunna, Krishna DT, A.P, India. Assistant Professor, Dept of ECE, IIIT, Rgukt-Nuzvid, A.P, India.
Pages
10-13
Abstract
A hypothesized conflict-free address scheme which is efficient for arbitrary point memory-based fast Fourier transform (FFT) processor was exhibited in this paper. In the proposed scheme, a high radix decomposition method was utilized for reducing the levels of computation and small radix connected multipath-delay-commutator butterfly units were adopted to eliminate the complexity of the computation engine as well. Several important functions of memory-based FFT processor were combined together, including the continuous-flow mode, variable computation size and conflict-free address scheme. Moreover, a prime factor algorithm was employed to decrease the multiplications and the twiddle factor storage when there subsist prime factors in the decomposition. At last, a unified Winograd Fourier transform algorithm (WFTA) butterfly core was designed for the small 2, 3, 4, 5 point DFTs to reduce the computation complexity further. Keywords - Conflict-free address scheme, long-term evolution (LTE), memory-based fast Fourier transform (FFT) processor, prime factor algorithm (PFA), Winograd algorithm.
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