DOIONLINE 
DOIONLINE Publish In |
International Journal of Electrical, Electronics and Data Communication (IJEEDC)-IJEEDC |
 Journal Home Volume Issue |
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Issue |
Volume-6,Issue-9 ( Sep, 2018 ) | |||||||||
Paper Title |
Novel Mantissa Similarity Investigator for Path-Delay Reduction of Product Mantissa Calculation | |||||||||
Author Name |
Marcus Lloyde George | |||||||||
Affilition |
Dept. Electrical and Computer Engineering, University of the West Indies, St. Augustine, Trinidad and Tobago | |||||||||
Pages |
74-81 | |||||||||
Abstract |
Floating point multiplication is a very important component of many engineering applications such as signal processing, video processing and image processing. In floating point multiplication, the mantissa calculation operation caters for the majority of time for the process. Because of this it is important to consider the speed up of the mantissa multiplication process in order to speed up systems that utilize floating point multiplication. This paper presents the development of a novel Mantissa Similarity Investigator (MSI) which can be interfaced to any product mantissa calculator to reduce the path delay of the multiplication operation. The system was synthesized for a variety of FPGA targets using Xilinx ISE Design Suite 14.7 Commercial Edition. The Mantissa Similarity Investigator (MSI) was interfaced to a Mantissa Calculator developed for this project, to form a complete novel MSI-Interfaced Mantissa Calculator. The path delay of this system was compared with existing implementations of 24-bit, 53-bit, 113-bit and 237-bit binary multipliers which represent mantissa multiplication at various precision levels. The novel MSI-Interfaced Mantissa Calculator achieved shorter path delay than its existing counter paths reviewed. Keywords - Arithmetic Logic Unit; Arithmetic Circuits; Binary Multiplier; Floating-Point Multiplier; Arithmetic Logic; FPGAs in Arithmetic. | |||||||||
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