DOIONLINE 
DOIONLINE Publish In |
International Journal of Electrical, Electronics and Data Communication (IJEEDC)-IJEEDC |
 Journal Home Volume Issue |
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Issue |
Volume-6,Issue-9 ( Sep, 2018 ) | |||||||||
Paper Title |
Fault Tolerance Improvement of The Secured Circuits | |||||||||
Author Name |
Ghania Ait Abdelmalek, Rezki Ziani, Rabah Mokdad | |||||||||
Affilition |
Department of Electronic, Mouloud Mammeri University, Tizi-Ouzou, Algeria Laboratoire de Physique et chimie quantique, Mouloud Mammeri University, Tizi-ouzou, Algeria | |||||||||
Pages |
50-52 | |||||||||
Abstract |
One of the major problems in testing a system-on-chip is dealing with the optimal choice of the test sequence. In this paper, we propose an efficient test sequence for TMR secure circuits. The test sequence is a high level method based on three pulsations. An extension to the sequence with one pulsation is proposed and by simulation results its effectiveness in achieving a higher fault tolerance interval is demonstrated. | |||||||||
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