DOIONLINE 
DOIONLINE Publish In |
International Journal of Electrical, Electronics and Data Communication (IJEEDC)-IJEEDC |
 Journal Home Volume Issue |
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Issue |
Volume-6,Issue-8 ( Aug, 2018 ) | |||||||||
Paper Title |
Design of n-bit Tree based Comparator | |||||||||
Author Name |
Mahalakshmi K S, Jayashree H V | |||||||||
Affilition |
Dept. of ECE, PESIT, Bengaluru, India | |||||||||
Pages |
53-55 | |||||||||
Abstract |
Reversible logic gates gain attention in recent years due to its low power consumption ability. It is used in advance computing, DNA computing, quantum computation, low power CMOS design and nanotechnology. In this paper an n-bit optimized tree based reversible comparator is proposed using existing reversible logic gates. The design is realized and the parameters garbage output, Ancilla/constant input, quantum cost and delay are calculated. The design is simulated using ISE simulator (Xilinx 14.7, spartan 6). Keyword - Reversible Gate, Quantum Cost, Ancilla Input, Garbage Output, Comparator. | |||||||||
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