DOIONLINE 
DOIONLINE Publish In |
International Journal of Electrical, Electronics and Data Communication (IJEEDC)-IJEEDC |
 Journal Home Volume Issue |
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Issue |
Volume-6,Issue-7 ( Jul, 2018 ) | |||||||||
Paper Title |
Testing of Stuck at Fault in Digital Circuits at Register Transfer Logic (RTL) | |||||||||
Author Name |
Naina A. Udge, S. A. Ladhake, P. D. Gawande | |||||||||
Affilition |
Principal, SIPNA COET, Amravati (M.H.) Associate Professor, SIPNA COET, Amravati (M.H.) | |||||||||
Pages |
55-58 | |||||||||
Abstract |
Semiconductor Integrated Circuits (ICs) can have millions of digital circuits which can translate to billions of transistors. Lots of effort has been put into Electronic Design Automation (EDA) systems and Design for Test (DFT) techniques to manage the development and application of digital circuit testing. In the beginning these software programs and DFT techniques used the Stuck at Fault Model.With a stuck at fault model we are applying a structural test approach. Instead of testing all combination of 1’s and 0’s to a VLSI device, we will test with a reduced set of test vectors. Stuck at Fault Models operate at the logic model of digital circuits. We will detect the stuck-at fault using the concept of textio. Keywords - Stuck-atfaults; Fault coverage; Testpoints; Validation Sets; Textio | |||||||||
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