DOIONLINE 
DOIONLINE Publish In |
International Journal of Electrical, Electronics and Data Communication (IJEEDC)-IJEEDC |
 Journal Home Volume Issue |
||||||||
Issue |
Volume-6,Issue-7 ( Jul, 2018 ) | |||||||||
Paper Title |
Significance of Gate Controllability in Electrically Doped Gate All Around TFET ED-GAA-TFET with Dimension Analysis | |||||||||
Author Name |
Priyanka Suman, Dheeraj Sharma, Alemienla Lemtur, Jyoti Patel | |||||||||
Affilition |
Electronics and Communication Engineering Discipline, PDPM-Indian Institute of Information Technology, Design and Manufacturing Jabalpur 482005, India | |||||||||
Pages |
47-51 | |||||||||
Abstract |
Nano wire architecture strengthens the gate electrostatic control over the intrinsic channel region and dopingless TFET using polarity based concept is known to have reduced fabrication complexity and eliminate random dopant fluctuation (RDF). To avail the aforesaid advantages, we have introduced for the first time a 3D cylindrical electrically doped gate all around TFET (ED-GAA-TFET). In our work, the proposed device ED-GAA-TFET, not only achieves a good ON-state current of 1.6×10-5 A/μm, but also suppresses the ambipolar conduction (5.52×10-16 A/μm) completely. This is done here, by incorporating spacer 1.5 nm and 5 nm at the source edge and drain edge respectively with respect to channel gate as, source spacer (SS) determines tunneling probability and drain spacer (DS) arrests negative conductance. Simultaneously, Subthreshold swing (28mV/dec) and OFF-state current (5.52×10-16 A/μm) show it's suitability for low power application by providing low leakage current and low static power dissipation. Further, optimization is done to reduce fabrication complexity in terms of device diameter of intrinsic substrate, spacer lengths between source and gate (LSS) & drain and gate (LDS) and finally, the channel length of ED-GAA-TFET. Keywords - ED-GAA-TFET, random dopant fluctuation, electrically doped. | |||||||||
| View Paper | ||||||||||
