DOIONLINE 
DOIONLINE Publish In |
International Journal of Electrical, Electronics and Data Communication (IJEEDC)-IJEEDC |
 Journal Home Volume Issue |
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Issue |
Volume-2,Issue-10 ( Oct, 2014 ) | |||||||||
Paper Title |
On Chip Generation Of Functional Tests For High Transition Faults Using Fixed Hardware | |||||||||
Author Name |
K. B.Meena Kumari, V.Thrimurthulu, N.P.Dharani | |||||||||
Affilition |
PG Scholar, Dept of VLSISD, CR Engineering College, Tirupati, Chittor, AP, India Prof & HOD, Dept of ECE, CR Engineering College, Tirupati, Chittor, AP, India Asst Prof, Dept of ECE, CR Engineering College, Tirupati, Chittor, AP, India | |||||||||
Pages |
77-81 | |||||||||
Abstract |
In this proposed method we are test the one combinational circuit. Here this combinational circuit having 36-bit input and 7-bit output. ISCAS-85 C432 27-channel interrupt controller is a combinational benchmark circuit. This paper described an on-chip test generation method for functional broadside tests. The hardware was based on the application of primary input sequences initial from a known reachable state, thus using the circuit to produce additional reachable states. Random primary input sequences were changed to avoid repeated synchronization and thus yield varied sets of reachable states. The hardware structure was simple and fixed, and it was tailored to a given circuit only through the following parameters: the length of the LFSR used for producing a random primary input sequence; the length of the primary input sequence; the specific gates used for modifying the random primary input sequence; the particular gate used for selecting applied tests; and the seeds for the LFSR. With the proposed on-chip test generation method, the circuit is used for generate reachable states for the duration of test application. This alleviates the want to compute reachable states offline. | |||||||||
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