DOIONLINE 
DOIONLINE Publish In |
International Journal of Electrical, Electronics and Data Communication (IJEEDC)-IJEEDC |
 Journal Home Volume Issue |
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Issue |
Volume-6,Issue-6 ( Jun, 2018 ) | |||||||||
Paper Title |
High-Speed Pipelined 8-Bit RISC Processor Design using Verilog HDL on FPGA | |||||||||
Author Name |
B. Sajidha Thabassum, Triveni, Darshan B.B., Devanabanda Kousik, Diwakar S Mattukumilli | |||||||||
Affilition |
Assistant Professor, Department of Electronics and Communication Engineering, Dr. Ambedkar Institute of Technology, Bengaluru, India Student, Department of Electronics and Communication Engineering, Dr. Ambedkar Institute of Technology, Bengaluru, India | |||||||||
Pages |
43-46 | |||||||||
Abstract |
Because of its capability to extraordinarily quicken a wide variety applications, reconfigurable computing has turned into a subject of a lot of research. Its key component is the capacity to perform calculations in equipment to build execution, while holding a great part of the adaptability of a product arrangement. In this design of 8-bit RISC processor using Harvard architecture, we give a review of the architecture of reconfigurable computing machines, and the software that objectives these machines, code for the modules and underscore on execution improvement pipelining procedure. At long last, we test the speed of the processor by running all kind of instructions. Keywords - Reconfigurable Computing, RISC, Pipeline-Technique, FPGA, Harvard Architecture. | |||||||||
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