DOIONLINE 
DOIONLINE Publish In |
International Journal of Electrical, Electronics and Data Communication (IJEEDC)-IJEEDC |
 Journal Home Volume Issue |
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Issue |
Volume-6,Issue-6 ( Jun, 2018 ) | |||||||||
Paper Title |
Design of CMOS Multistage High Gain Differential Amplifier using Cadence | |||||||||
Author Name |
Shivani M Aderao, Sushmakejgir | |||||||||
Affilition |
PG Student, Associate Professor, Electronics Engineering, Shri Guru Gobind Singhji Institute of Engineering and Technology | |||||||||
Pages |
50-53 | |||||||||
Abstract |
In this paper behavior of multiple energy storage elements of Op-amp is observed. Initially a two stage Op-amp is designed using CMOS technology in VLSI. Designed Op-Amp consists of differential amplifier & gain amplifier. The initial stage of differential amplifier removes the noise and only amplifies the actual signal. Since the amplified signal does not meet Op-amp requirements a gain amplifier is used for amplification. 2nd stage is a common source amplifier which is used to increase the gain. Keywords - Cadence gpdk090, gpdk180, Differential Amplifier, Common Source Amplifier, Current Mirror circuit. | |||||||||
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