DOIONLINE 
DOIONLINE Publish In |
International Journal of Electrical, Electronics and Data Communication (IJEEDC)-IJEEDC |
 Journal Home Volume Issue |
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Issue |
Volume-2,Issue-9 ( Sep, 2014 ) | |||||||||
Paper Title |
Reusable And Reconfigurable Approach To Functional Verification Of A Chip | |||||||||
Author Name |
S. Madhuri | |||||||||
Affilition |
Electronics & Instrumentation NIT Warangal | |||||||||
Pages |
31-33 | |||||||||
Abstract |
Verification is a process used to demonstrate the functional correctness of a design. Also called logic verification or simulation. This paper demonstrates the functional verification planning process for creating a reusing and reconfigurable verification systems (test bench) which can be used to verify different versions of a component design with minimum changes in the verification environment by using minimum components for creating verification environment. | |||||||||
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