DOIONLINE

DOIONLINE NO - IJASEAT-IRAJ-DOIONLNE-310

Publish In
International Journal of Advances in Science, Engineering and Technology(IJASEAT)-IJASEAT
Journal Home
Volume Issue
Issue
Volume-1,Issue-2  ( Oct, 2013 )
Paper Title
A Low Leakage Nanoscale CMOS Memory Cell With Virtual Grounding
Author Name
L.Krishnaveni, T.Venkatasridhar
Affilition
M.tech,VLSI, ASCET, Gudur, Andhra Pradesh, India, M.tech,MIETE, Associative professor Department of ECE ASCET Gudur, Andhra Pradesh, India
Pages
51-54
Abstract
In this paper we are going to modify the Schmitt Trigger based SRAM for the purpose of more reduced power,leakage & area than the existing type of designs as well as the new design which is combined of virtual grounding with read Error Reduction Logic is compared with the existing technologies & the nanometer technology is also improved for the purpose of much improved reduction of area, leakage & power factors than the Schmitt Trigger based SRAM Designs the simulations were done using microwind & DSCH results
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