DOIONLINE 
DOIONLINE Publish In |
International Journal of Advances in Science, Engineering and Technology(IJASEAT)-IJASEAT |
 Journal Home Volume Issue |
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Issue |
Volume-1,Issue-3 ( Jan, 2014 ) | |||||||||
Paper Title |
Design Of High Performance 16-Bit Brent Kung Adder Using Static Cmos Logic Style In 45nm Cmos Ncsu Free Pdk | |||||||||
Author Name |
Nirav Desai | |||||||||
Affilition |
ITM Universe, Vadodara, Gujarat | |||||||||
Pages |
33-35 | |||||||||
Abstract |
High performance microprocessor units require high performance adders and other arithmetic units. Modern microprocessors are however 32-bits or 64-bits as that is the minimum required for floating point arithmetic as per the IEEE 754 Standard. 8-bit and 16-bit arithmetic processors are normally found in micro-controller applications for embedded systems where high speed is important but low power constraints dominate system design. A good metric of performance on such designs would be the power-delay product (or equivalently energy per bit.) Many designs give a high speed at the cost of more power or low power at the cost of low speed. The design of a 16-bit Brent Kung adder presented here has the lowest delay (among the adders compared, Table 2) and also the lowest power-delay product (among the adders compared, Table 2) in similar technology nodes. The design makes use of logical effort [2] based sizing of transistors and advanced layout techniques like fingering and inter-digitating to reduce the self-loading of the transistors from parasitic transistor capacitances. | |||||||||
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