DOIONLINE 
DOIONLINE Publish In |
International Journal of Advances in Science, Engineering and Technology(IJASEAT)-IJASEAT |
 Journal Home Volume Issue |
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Issue |
Volume-1,Issue-2 ( Oct, 2013 ) | |||||||||
Paper Title |
Design, Simulation And Comparison Of 256-Bits 64-Points Radix-4 And Radix-2 Algorithms | |||||||||
Author Name |
G Sudha Kiran, P Brundavani | |||||||||
Affilition |
Post Graduate in VLSI, Annamacharya Institute of Technology and Sciences, Rajampet Assistant Professor, Department of ECE, Annamacharya Institute of Technology and Sciences, Rajampet | |||||||||
Pages |
64-67 | |||||||||
Abstract |
Technical device uses and users are rapidly increasing, besides this the device accuracy and fastness is more important requirement. In the view of this, present project came into existence and its focus on the development of the Fast Fourier Transform (FFT) algorithm, based on Decimation-In- Time (DIT) domain, Radix-4 algorithm, which uses VHDL as a design entity and their Synthesis by Xilinx Synthesis Tool of 8.1 version. The synthesis results show that the computation for calculating the 256 bits 64-point FFT is efficient in terms of speed. | |||||||||
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