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International Journal of Advances in Science, Engineering and Technology(IJASEAT)-IJASEAT
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Volume Issue
Volume-1,Issue-2  ( Oct, 2013 )
Paper Title
New Leakage Reduction Techniques
Author Name
P.S.G. Sridevi, P.V.K. Chaitanya
( M.Tech)ECE, M.Tech Assistant Professor
This paper aims at designing SRAM memories with less power dissipation by reducing gate leakage current and sub threshold leakage current. The IWLVC cell structure results in reduced gate voltages for the NMOS pass transistors, and thus lower the gate leakage current. It reduces the sub-threshold leakage current by increasing the ground level during the idle (inactive) mode. The PPSRAM cell structure makes use of PMOS pass transistors to lower the gate leakage current. The SKPP-SRAM cell structure uses the Sleepy Keeper transistors which reduces the Static Power of the circuit. Compared to a conventional SRAM cell, the IWLVC cell structure decreases the total gate leakage current and also the idle power and increases the access time while the PPSRAM cell structure reduces the total gate leakage current and the idle power but with no access time degradation. SKPP-SRAM reduces the Static Power of the circuit
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