DOIONLINE 
DOIONLINE Publish In |
International Journal of Advances in Electronics and Computer Science-IJAECS |
 Journal Home Volume Issue |
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Issue |
Volume-4,Issue-1 ( Jan, 2017 ) | |||||||||
Paper Title |
Built-in Self-Test Repair (BISTR) Technique For Radom Access Memories (RAMs) | |||||||||
Author Name |
A. Sruthi, V.R. Sheshagiri Rao | |||||||||
Affilition |
Institute of aeronautical engineering, Hyderabad | |||||||||
Pages |
22-24 | |||||||||
Abstract |
Built-in self-test repair (BISTR) technique has been most widely used to test repair embedded random access memories (RAMs). This paper proposes a reconfigurable BISTR (ReBISTR) scheme totest repairing RAMs with different sizes and redundancy organizations. An efficient redundancy BIST algorithm is proposed to allocate redundancies of defective RAMs. In the ReBISTR, a reconfigurable built-in self-test and test repairredundancy analysis is (ReBIRA) design circuit is to perform the redundancy algorithm for various RAMs. Also, an adaptive reconfigurable methodology is proposed to reduce the test repair setup time when the RAMs are operated in normal mode. Due to the complexity of memory architectures, the possibility of occurring manufacturing defects is high. Hence memory testing is necessary. Built inSelf- Testrepair (BISTR) has been proven to be most cost-effective and widely used solutions for memory testing. BISTR technique is used to reduce test repair time. The design architecture is simulatedin Xilinx ISE 14.7 tools. Keywords— SOC, BIST, BISTR, Test Pattern Generator, FPGA. | |||||||||
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