DOIONLINE 
DOIONLINE Publish In |
International Journal of Advances in Electronics and Computer Science-IJAECS |
 Journal Home Volume Issue |
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Issue |
Volume-3,Issue-7 ( Jul, 2016 ) | |||||||||
Paper Title |
Design And Implementation Efficient DCT Architecture | |||||||||
Author Name |
Jagriti Sahu | |||||||||
Affilition |
Y C College of Engineering, Nagpur, India | |||||||||
Pages |
74-78 | |||||||||
Abstract |
Two dimensional DCT takes a very important role in JPEG image and video compression. Architecture and Verilog design of 2-D DCT is described in this paper. Multiplier-free approximate DCT transforms have been proposed that that offer high compression performance at very low hardware complexity. The approximation can be realized using VLSI hardware using additions and subtractions only leading to decrease in chip area and power consumption compared to other DCT transforms. This paper comprises of a 8-point DCT approximation with 14 addition operation. The proposed approximation possesses low complexity in terms of computation and is compared to other DCT approximation in terms of algorithm complexity. Index Terms— Approximate DCT, image compression, low complexity algorithms, low power consumption, multiplier free approximation. | |||||||||
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