DOIONLINE 
DOIONLINE Publish In |
International Journal of Advances in Electronics and Computer Science-IJAECS |
 Journal Home Volume Issue |
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Issue |
Volume-2, Issue-8 ( Aug, 2015 ) | |||||||||
Paper Title |
Design And Analysis Of Finfet Based High Performance 1-Bit Half Adder-Half Subtractor Cell | |||||||||
Author Name |
Ruchi Dantre, Sudha Yadav | |||||||||
Affilition |
M-Tech, Dept. of ECE, 2Sr. Assistant Professor, Dept. of EEE, Amrita school of Engineering, Bangalore, India | |||||||||
Pages |
122-126 | |||||||||
Abstract |
Abstract- we are moving towards the era of minimization of transistor size, short channel effects (SCEs) are becoming major concern. Double gate FinFETs are emerging transistors, which gives better SCEs performance compared to conventional Mosfet transistors .Adders and sub-tractors are very basic components in computation. Most of the operations such as multiplication, division, ripple carry addition etc. require Adder and sub-tractor as a basic building block. The efficiency of any system depends on the performance of internal components. If internal components satisfy the criteria of area, power and delay, the system will always be a efficient system. The adders and sub-tractors are mainly used in (arithmetic and logical units) ALUs. In this paper, area and (power delay product) PDP efficient common Half Adder-Half sub-tractor cell design is presented at 32nm technology. Keywords- Alu; Double Gate Finfet (Dgfinfet); Delay; Half Adder; Half Subtractor; High Performance; Low Power. | |||||||||
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