DOIONLINE 
DOIONLINE Publish In |
International Journal of Advances in Electronics and Computer Science-IJAECS |
 Journal Home Volume Issue |
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Issue |
Volume-2, Issue-6 ( Jun, 2015 ) | |||||||||
Paper Title |
Implementation Of Area-Delay-Power Efficient Adder For Unsigned Integer Multiplier | |||||||||
Author Name |
Nalina R, Ashwini S S, M Z Kurian | |||||||||
Affilition |
M.Tech, Student, (VLSI & Embedded Systems), SSIT, Tumkur, Karnataka, India Assistant professor, Department of ECE, SSIT, Tumkur, Karnataka, India Professor and Head, Department of ECE, SSIT, Tumkur, Karnataka, India | |||||||||
Pages |
86-88 | |||||||||
Abstract |
Multiplication and addition are most widely and oftenly used arithmetic computations performed in all digital signal processing applications. Multiplication is the basic arithmetic operation which is present in many part of the digital computer especially in signal processing systems such as graphics and computation system. It requires substantially more hardware resources and processing time than addition and subtraction. In fact, 8.72% of all the instruction in typical processing units is multiplication. This paper deals with the basic multiplier that is shift and add multiplier. Accurate operation of the shift and add multiplier is mainly influenced by the performance of the adder. So performance of the adder enhances the performance of the multiplier. Hence, to design a better architecture the basic adder blocks must have reduced delay time consumption and area efficient architectures. This paper involves the implementation of an adder for shift and add multiplier in terms of area delay and power. In this method, the carry-select operation is scheduled before the calculation of final-sum, which is different from the conventional approach. Keywords – Square Root Carry Select Adder using Binary to Excess-1(SQRT CSLA using BEC-1) | |||||||||
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