DOIONLINE 
DOIONLINE Publish In |
International Journal of Advances in Electronics and Computer Science-IJAECS |
 Journal Home Volume Issue |
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Issue |
Volume-2, Issue-5 ( May, 2015 ) | |||||||||
Paper Title |
Verilog Based Design Of High Performance Data Access Amba Memory Controller | |||||||||
Author Name |
Shobha R Hadimani, Panchami | |||||||||
Affilition |
M.Tech, Department of ECE, VTU University, MITE Moodbidre, Karnataka Assistant Professor, Department of ECE, VTU University, MITE Moodbidre, Karnataka | |||||||||
Pages |
88-91 | |||||||||
Abstract |
In this paper, an Advanced Microcontroller Bus Architecture (AMBA) compliant memory controller is designed for system memory control with the main memory consisting of SRAM, ROM and Dual port CACHE. As microprocessor performance has improved in recent years, it has become increasingly important to provide a high-bandwidth, low-latency memory subsystem to achieve the full performance potential of these processors. Dual port Caches have been used extensively to patch over this mismatch. The memory controller is the part of the system that, well, controls the memory. The aim is develop an architecture, design, and test AMBA AHB compliant Memory Controller for ARM based EMBEDDED platforms. Memory access time is reduced to a great extent by using AHB protocol thereby increasing the overall performance of the memory controller. Keywords—ARM, AMBA, AHB BUS, Memory controller | |||||||||
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