DOIONLINE 
DOIONLINE Publish In |
International Journal of Advances in Electronics and Computer Science-IJAECS |
 Journal Home Volume Issue |
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Issue |
Volume-7,Issue-7 ( Jul, 2020 ) | |||||||||
Paper Title |
A Review on Verification of APIs using SystemVerilog and UVM | |||||||||
Author Name |
Ravindra Babu, Gagana P, M Uttarakumari | |||||||||
Affilition |
Cypress Semiconductor, Bengaluru, India RV College of Engineering, Bengaluru, India RV College of Engineering, Bengaluru, India | |||||||||
Pages |
20-25 | |||||||||
Abstract |
With the rapid development of SoCs, manufacturing technologies and computer aided design (CAD) tools, design of SoCs is becoming complex than before. As the design becomes complex, verification time grows exponentially. Therefore, it is required to reduce the verification time under time to market pressure. Universal Verification Methodology (UVM) makes this possible by providing a library of base classes which can be used for the required functionality. In this paper, a review of verification of APIs using SystemVerilog and UVM is presented. Keywords - SystemVerilog, UVM, Coverage, APIs. | |||||||||
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