Publish In |
International Journal of Advances in Electronics and Computer Science-IJAECS |
Journal Home Volume Issue |
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Issue |
Volume-5,Issue-2 ( Feb, 2018 ) | |||||||||
Paper Title |
High-Level Optimizations for High-Level Synthesis | |||||||||
Author Name |
Michael Dossis, Georgios Dimitriou | |||||||||
Affilition |
TEI of Western Macedonia/University of Thessaly ,University of Thessaly | |||||||||
Pages |
49-56 | |||||||||
Abstract |
The rapidly increasing complexity of computer hardware makes impossible to design using directly HDLs. High-level synthesis can automatically deliver optimal HDL codes from high-level programming language code. Therefore, it becomes easier to design coprocessors, accelerators, and, in general, special-purpose hardware, in project time. Furthermore, high-level compiler optimizations improve the quality of generated hardware descriptions in terms of performance and size. Our high-level optimizations transform the input code, in order to generate high-performance output hardware description. In this paper, we discuss high-level compiler-based optimizations for high-level synthesis, such as loop pipelining in the front end of the prototype C-Cubed synthesis tool. Moreover, a novel pipelining technique that minimizes the area of the pipeline prologue and epilogue, is analyzed. Finally, we evaluate our optimizations with synthesis results of the Livermore loops and Mpeg2 open-source codes. Index Terms - high-level synthesis; formal hardware synthesis; compilers; compiler optimizations; loop transformations; loop pipelining; programming languages; hardware description languages; RTL design. | |||||||||
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