DOIONLINE 
DOIONLINE Publish In |
International Journal of Advance Computational Engineering and Networking (IJACEN)-IJACEN |
 Journal Home Volume Issue |
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Issue |
Volume-4, Issue-10 ( Oct, 2016 ) | |||||||||
Paper Title |
CVDR Algorithm For Asynchronous Network on Chip Design | |||||||||
Author Name |
Rabab Ezz-Eldin, Magdy A. El-Moursy, Hesham F. A. Hame | |||||||||
Affilition |
Electrical Engineering Department Beni-Suef University Beni-Suef, Egypt Mentor Graphics Corporation, Microelectronics Department, Electronics Research Institute (ERI), Cairo, Egypt Electrical Engineering Department Minia University, El-Minia, Egypt | |||||||||
Pages |
25-31 | |||||||||
Abstract |
To elucidate the influence of process variation on Network on Chip (NoC) design, all of router, interconnect and routing algorithm are implemented as key elements in 2D-Mesh topology. The delay variation is the main motivation to crumble the performance of routing algorithms with technology scales down. To avert the influence of process variation and congestion for asynchronous NoC design, a novel routing algorithm is presented. Congestion and process Variation Delay aware Routing (CVDR) algorithm is proposed as adaptive approach. At various traffic patterns, the improvement of CVDR algorithm as compared to different routing algorithms under process variation conditions is measured. CVDR algorithm performs better significantly than different routing algorithms, even under the presence of a process variation. Keywords- NoC; Asynchronous; Router; Interconnect; Process Variation; Routing Algorithms. | |||||||||
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