DOIONLINE 
DOIONLINE Publish In |
International Journal of Advance Computational Engineering and Networking (IJACEN)-IJACEN |
 Journal Home Volume Issue |
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Issue |
Volume-3, Issue-9 ( Sep, 2015 ) | |||||||||
Paper Title |
Design And Verification Of Network-On-Chip Router Architecture | |||||||||
Author Name |
Deepak S, Divyaprabha, M Z Kurian | |||||||||
Affilition |
M.Tech, Student, 2Associate professor, Professor and Head Department of ECE, SSIT, Tumkur, India | |||||||||
Pages |
73-76 | |||||||||
Abstract |
The scaling of microchip technologies has enabled large scale system-on-chip (SoC). Network-on-chip (NoC) research addresses global communication in SoC, involving (i) a move from computation-centric to communication-centric design and (ii) the implementation of scalable communication structures. NoC designs are based on compromise of latency and power dissipation usually defined at design time. In this paper, a novel cost-effective and low-latency wormhole router for packet switched NoC design has been proposed. Keywords- Network-on-Chip, Router, Arbiter, GALS. | |||||||||
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