DOIONLINE 
DOIONLINE Publish In |
International Journal of Advance Computational Engineering and Networking (IJACEN)-IJACEN |
 Journal Home Volume Issue |
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Issue |
Volume-1,Issue-8 ( Oct, 2013 ) | |||||||||
Paper Title |
A Novel And Efficient FFT Design Using Vedic Principles | |||||||||
Author Name |
Pasuluri Bindu Swetha, V.J.K.Kishor Sonti, Raghavendra Rao | |||||||||
Affilition |
Assistant Professor1, 2, Dept. of E.C.E., Software Engineer3 Stanley College of Engineering & Technology for Women1, Abids, Hyderabad Sathyabama University 2 Chennai, India | |||||||||
Pages |
05-09 | |||||||||
Abstract |
Vedic Mathematics is the ancient methodology of Indian mathematics, which has a unique technique of calculations based on 16 Sutras (Formulae). A high speed complex multiplier design and FFT application of it using Vedic Mathematics is presented in this paper. The idea for designing the multiplier and adder/subtractor unit is adopted from ancient Indian mathematics "Vedas". On account of those formulas, the partial products and sums are generated in one step which reduces the carry propagation from LSB to MSB. The ever increasing demand in enhancing the ability of processors to handle the complex and challenging processes has resulted in the integration of a number of processor cores into one chip. Still the load on the processor is not less in generic system. This load is reduced by supplementing the main processor with Co-Processors, which are designed to work upon specific type of functions like numeric computation, Signal Processing, Graphics etc. The speed of FFT depends greatly on the multiplier. This work is carried out on xilinix platform usig HDL programming.comparing with the conventional multiplier 50% of the slices are reduced for the vedic multipliers. | |||||||||
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