DOIONLINE 
DOIONLINE Publish In |
International Journal of Advance Computational Engineering and Networking (IJACEN)-IJACEN |
 Journal Home Volume Issue |
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Issue |
Volume-4, Issue-7 ( Jul, 2016 ) | |||||||||
Paper Title |
Reducing Energy Consumption In Noc By Data Encoding And Decoding Techniques | |||||||||
Author Name |
Chaithra K, Veena S Murthy | |||||||||
Affilition |
4th Sem, M.Tech, Dept of ECE, B N M Institute of Technology, Bangalore - 70 Associate Professor, Dept of ECE, B N M Institute of Technology, Bangalore - 70 | |||||||||
Pages |
58-61 | |||||||||
Abstract |
This paper mainly focuses on reducing the consumption of energy by the power dissipated links of a networkon- chip (NoC - Network on Chip) which starts to compete with the power dissipated by the other elements of the communication subsystem like the routers and the network interfaces (NIs). It provides a set of data encoding and decoding schemes aimed at reducing the power dissipated by the links of a NoC. The proposed schemes are general and transparent with respect to the underlying NoC Architectures. The paper provides few techniques to overcome the power dissipation by self switching activity and coupling switching activity. The proposed schemes has been implemented on Xilinx FPGA of Spartan-6 Family and it shows that 51% of power dissipation and 14% of energy consumption is saved and 15% area overhead in the NI is achieved without affecting the performance. Keywords— Network on Chip (NoC), power analysis, switching activity, Coupling switching activity, self switching activity. | |||||||||
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