DOIONLINE 
DOIONLINE Publish In |
International Journal of Advance Computational Engineering and Networking (IJACEN)-IJACEN |
 Journal Home Volume Issue |
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Issue |
Volume-4,Issue-2 ( Feb, 2016 ) | |||||||||
Paper Title |
Review On Implementation Of AES Algorithm For Device Based Encryption | |||||||||
Author Name |
Gaurav Berad, Ashish Jaggi, Vaibhav Jagadale | |||||||||
Affilition |
Computer Engineering, Department STES RMD SCE Pune, Singhad School of Engineering India Master Trainer,3Computer InstructorILS&FS ETS,Mumbai, India. | |||||||||
Pages |
75-78 | |||||||||
Abstract |
Recently, the number of electronic devices handling confidential information has increased. In these devices, encryption is applied to protect the confidential information. Therefore, technologies to incorporate cryptographic circuits into these cards have become important. This paper proposes a new hardware dedicated to a typical cryptograph. In the proposed AES dedicated hardware, by introducing an architecture suitable for each operation used for the encryption, highspeed processing and area reduction can be realized. Experimental results of which proposed hardware architecture is implemented on FPGA proved the validity of the proposed one. Keywords— Cryptography, Dedicated Hardware, FPGA implementation. | |||||||||
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