DOIONLINE 
DOIONLINE Publish In |
International Journal of Advance Computational Engineering and Networking (IJACEN)-IJACEN |
 Journal Home Volume Issue |
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Issue |
Volume-9,Issue-6 ( Jun, 2021 ) | |||||||||
Paper Title |
Implementation of 32-bit 5-stage Pipelined RISC Processor | |||||||||
Author Name |
Nayana Yerram, Deepak Ch | |||||||||
Affilition |
School of Electronics Engineering, VIT-AP University, Amaravati, Andhra Pradesh, India 522237 | |||||||||
Pages |
1-4 | |||||||||
Abstract |
A Reduced Instruction Set Computer or RISC has a small set of simple instruction exist in 8,16,32 and 64-bit, which are now used across a wide range of platforms. The low power technique, Pipelining is the process of executing the instructions in the orderly fashion. In this paper, 32-bit 5-stage pipelined RISC Processor is designed utilizing Verilog HDL. The objective of this paper is to execute 32-bit instructions set which is written using hardware description language (HDL) in pipeline process to lessen the power utilization. The processor is designed on Xilinx ISE Design Suite platform. Keywords - Reduced Instruction Set Computer (RISC), Low Power, Pipelining. | |||||||||
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